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this is information on a product in full production. august 2013 docid022028 rev 3 1/27 l6206q dmos dual full bridge driver datasheet - production data features ? operating supply voltage from 8 to 52 v ? 5.6 a output peak current r ds(on) 0.3 ? typ. value at t j = 25 c ? operating frequency up to 100 khz ? programmable high side overcurrent detection and protection ? diagnostic output ? paralleled operation ? cross conduction protection ? thermal shutdown ? undervoltage lockout ? integrated fast free wheeling diodes application ? bipolar stepper motor ? dual or quad dc motor description the l6206q device is a dmos dual full bridge driver designed for motor control applications, developed using bcdmultipower technology, which combines isolated dmos power transistors with cmos and bipolar circuits on the same chip. available in a vfqfpn48 7 x 7 package, the l6206q device features thermal shutdown and a non-dissipative overcurrent detection on the high side power mosfet s plus a diagnostic output that can be easily used to implement the overcurrent protection. figure 1. block diagram 9)4)31 [ pp ',1$ *$7( /2*,& 29(5 &855(17 '(7(&7,21 29(5 &855(17 '(7(&7,21 *$7( /2*,& 9&3 9%227 (1 $ ,1 $ ,1 $ (1 % ,1 % ,1 % 9 %227 9 9 96 $ 9 6 % 287 $ 287 $ 287 % 287 % 6(16( $ &+$5*( 3803 92/7$*( 5(*8/$725 7+(50$/ 3527(&7,21 9 %227 9 %227 9 9 %5,'*($ %5,'*(% 6(16( % 352*&/ % 2&' % 2&' $ 352*&/ $ 2&' $ 2&' % www.st.com
contents l6206q 2/27 docid022028 rev 3 contents 1 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . .11 4.4 thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 paralleled operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 output current capability a nd ic power dissipation . . . . . . . . . . . . . . 21 8 thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 electrical characteristics cur ves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
docid022028 rev 3 3/27 l6206q electrical data 27 1 electrical data 1.1 absolute maximum ratings 1.2 recommended operating conditions table 1. absolute maximum ratings symbol parameter test condition value unit v s supply voltage v sa = v sb = v s 60 v v od differential voltage between vs a , out1 a , out2 a , sense a and vs b , out1 b , out2 b , sense b v sa = v sb = v s = 60 v; v sensea = v senseb = gnd 60 v v ocda , v ocdb ocd pins voltage range -0.3 to +10 v v progcla , v progclb progcl pins voltage range -0.3 to +7 v v boot bootstrap peak voltage v sa = v sb = v s v s + 10 v v in ,v en input and enable voltage range -0.3 to +7 v v sensea , v senseb voltage range at pins sense a and sense b -1 to +4 v i s(peak) pulsed supply current (for each vs pin), internally limited by the overcurrent protection v sa = v sb = v s ; t pulse < 1 ms 7.1 a i s rms supply current (for each vs pin) v sa = v sb = v s 2.5 a t stg , t op storage and operating temperature range -40 to 150 c table 2. recommended operating conditions symbol parameter test condition min. max. unit v s supply voltage v sa = v sb = v s 8 52 v v od differential voltage between vs a , out1 a , out2 a , sense a and vs b , out1 b , out2 b , sense b v sa = v sb = v s ; v sensea = v senseb 52 v v sensea , v senseb voltage range at pins sense a and sense b pulsed t w < t rr -6 6 v dc -1 1 v i out rms output current 2.5 a t j operating junction temperature -25 +125 c f sw switching frequency 100 khz
pin connection l6206q 4/27 docid022028 rev 3 2 pin connection figure 2. pin connection (top view) 1. the exposed pad must be connected to gnd pin. am02556v1 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 epad out1a out1a gnd nc ocdb senseb senseb nc in1b in2b progclb enb vboot nc out2b out2b ocda sensea sensea nc in2a in1a progcla ena vcp nc out2a out2a out1b out1b nc nc nc nc nc nc vsa vsa nc nc vsb vsb nc nc gnd nc nc nc table 3. pin description pin name type function 43 in1a logic input bridge a logic input 1. 44 in2a logic input bridge a logic input 2. 45, 46 sensea power supply bridge a source pin. this pin must be connected to power ground directly or through a sensing power resistor. 48 ocda open-drain output bridge a overcurrent detection and t hermal protection pin. an internal open-drain transistor pulls to gnd w hen overcurrent on bridge a is detected or in case of thermal protection. 2, 3 out1a power output bridge a output 1. 6, 31 gnd gnd signal ground terminals. these pins are also used for heat dissipation toward the pcb. 10, 11 out1b power output bridge b output 1. 13 ocdb open-drain output bridge b overcurrent detection and t hermal protection pin. an internal open-drain transistor pulls to gnd w hen overcurrent on bridge b is detected or in case of thermal protection. 15, 16 senseb power supply bridge b source pin. this pin must be connected to power ground directly or through a sensing power resistor. 17 in1b logic input bridge b input 1
docid022028 rev 3 5/27 l6206q pin connection 27 18 in2b logic input bridge b input 2 19 progclb r pin bridge b overcurrent level programming. a resistor connected between this pin and ground sets the programmable current limiting value for bridge b. by connecting this pin to ground the maximum current is set. this pin cannot be left unconnected. 20 enb logic input bridge b enable. low logic level s witches off all power mosfets of bridge b. if not used, it must be connected to +5 v. 21 vboot supply voltage bootstrap voltage needed for driving the upper power mosfets of both bridge a and bridge b. 22, 23 out2b power output bridge b output 2. 26, 27 vsb power supply bridge b power supply voltage. it must be connected to the supply voltage together with pin vsa. 34, 35 vsa power supply bridge a power supply voltage. it must be connected to the supply voltage together with pin vsb. 38, 39 out2a power output bridge a output 2. 40 vcp output charge pum p oscillator output. 41 ena logic input bridge a enable. low logic level s witches off all power mosfets of bridge a. if not used, it must be connected to +5 v. 42 progcla r pin bridge a overcurrent level programming. a resistor connected between this pin and ground sets the programmable current limiting value for bridge a. by connecting this pin to ground, the maximum current is set. this pin cannot be left unconnected. table 3. pin description (continued) pin name type function
electrical characteristics l6206q 6/27 docid022028 rev 3 3 electrical characteristics v s = 48 v, t a = 25 c, unless otherwise specified. table 4. electrical characteristics symbol parameter test condition min. typ. max. unit v sth(on) turn-on threshold 6.6 7 7.4 v v sth(off) turn-off threshold 5.6 6 6.4 v i s quiescent supply current all bridges off; t j = -25 c to 125 c (1) 510ma t j(off) thermal shutdown temperature 165 c output dmos transistors r ds(on) high-side switch on resistance t j = 25 c 0.34 0.4 ? t j =125 c (1) 0.53 0.59 low-side switch on resistance t j = 25 c 0.28 0.34 t j =125 c (1) 0.47 0.53 i dss leakage current en = low; out = v s 2ma en = low; out = gnd -0.15 ma source drain diodes v sd forward on voltage i sd = 2.5 a, en = low 1.15 1.3 v t rr reverse recovery time i f = 2.5 a 300 ns t fr forward recovery time 200 ns logic input v il low level logic input voltage -0.3 0.8 v v ih high level logic input voltage 2 7 v i il low level logic input current gnd logic input voltage -10 a i ih high level logic input current 7 v logic input voltage 10 a v th(on) turn-on input threshold 1.8 2 v v th(off) turn-off input threshold 0.8 1.3 v v th(hys) input threshold hysteresis 0.25 0.5 v switching characteristics t d(on)en enable pin to out, turn on delay time (2) i load = 2.5 a, resistive load 100 250 400 ns t d(on)in input pin to out, turn on delay time i load = 2.5 a, resistive load (deadtime included) 1.6 s t rise output rise time (2) i load = 2.5 a, resistive load 40 250 ns t d(off)en enable pin to out, turn off delay time (2) i load = 2.5 a, resistive load 300 550 800 ns
docid022028 rev 3 7/27 l6206q electrical characteristics 27 figure 3. switching characteristic definition t d(off)in input pin to out, turn off delay time i load = 2.5 a, resistive load 600 ns t fall output fall time (2) i load = 2.5 a, resistive load 40 250 ns t dt deadtime protection 0.5 1 s f cp charge pump frequency -25 c < t j < 125 c 0.6 1 mhz overcurrent detection i s over input supply overcurrent detection threshold -25 c < t j < 125 c; r cl = 39 k ? -25 c < t j < 125 c; r cl = 5 k ? -25 c < t j <125 c; r cl = gnd 0.57 4.42 5.6 a a a r opdr open-drain on resistance i = 4 ma 40 60 ? t ocd(on) ocd turn-on delay time (3) i = 4 ma; c en < 100 pf 200 ns t ocd(off) ocd turn-off delay time (3) i = 4 ma; c en < 100 pf 100 ns 1. tested at 25 c in a restricted range and guaranteed by characterization. 2. see figure 3 . 3. see figure 4 . table 4. electrical characteristics (continued) symbol parameter test condition min. typ. max. unit am02557v1 v th(on) v th(off) 90% 10% en i out t t t fall t d(off)en t rise t d(on)en d01in1316
electrical characteristics l6206q 8/27 docid022028 rev 3 figure 4. overcurrent de tection timing definition am02558v1 ocd threshold 90% 10% i out v ocd t t t ocd(off) t ocd(on)
docid022028 rev 3 9/27 l6206q circuit description 27 4 circuit description 4.1 power stages and charge pump the l6206q device integrates two independent power mos full bridges. each power mos has an r ds(on) = 0.3 ? (typical value at 25 c) with intrin sic fast freewheeling diode. cross conduction protection is implemented by using a deadtime (t dt = 1 s typical value) set by an internal timing circuit between the turn-off and turn-on of two power mosfets in one leg of a bridge. pins vs a and vs b must be connected together to the supply voltage (v s ). using an n-channel power mosfet for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. the bootstrapped supply (v boot ) is obtained through an internal oscillator and few external components to realize a charge pump circuit, as shown in figure 5 . the oscillator output (pin vcp) is a square wave at 600 khz (typically) with 10 v amplitude. recommended values/part numbers for the charge pump circuit are shown in table 5 . figure 5. charge pump circuit 4.2 logic inputs pins in1 a , in2 a , in1 b , in2 b , en a , and en b are ttl/cmos and c compatible logic inputs. the internal structure is shown in figure 6 . the typical values for turn-on and turn-off thresholds are respectively v th(on) = 1.8 v and v th(off) = 1.3 v. pins en a and en b are commonly used to implement overcurrent and thermal protection by connecting them respectively to the outputs ocd a and ocd b , which are open-drain outputs. if this type of connection is chosen, particular care needs to be taken in driving these pins. two configurations are shown in figure 7 and figure 8 . if driven by an open- drain (collector) structure, a pull-up resistor r en and a capacitor c en are connected as table 5. charge pump external component values component value c boot 220 nf c p 10 nf r p 100 ? d1 1n4148 d2 1n4148 am02559v1 d2 c boot d1 r p c p v s vs a vcp vboot vs b
circuit description l6206q 10/27 docid022028 rev 3 shown in figure 7 . if the driver is a standard push-pull structure the resistor r en and the capacitor c en are connected as shown in figure 8 . the resistor r en should be chosen in the range from 2.2 k ? to 180 k ? . recommended values for r en and c en are respectively 100 k ? and 5.6 nf. more information on selecting the values can be found in section 4.3: non-dissipative overcurren t detection and protection . figure 6. logic inputs internal structure figure 7. en a and en b pins open collector driving figure 8. en a and en b pins push-pull driving $0y 9 (6' 3527(&7,21 $0y 9 9 23(1 &2//(&7 25 287387 5 (1 & (1 (1 $ ru(1 % $0y 9 386+38// 287387 5 (1 & (1 (1 $ ru(1 %
docid022028 rev 3 11/27 l6206q circuit description 27 4.3 non-dissipative overcurrent detection and protection the l6206q device integrates an overcurrent de tection circuit (ocd). with this internal overcurrent detection, the external current sens e resistor normally used and its associated power dissipation are eliminated. figure 9 shows a simplified schematic of the overcurrent detection circuit for bridge a. bridge b is provided with an analogous circuit. to implement the overcurrent detection, a sensing element that delivers a small but precise fraction of the output current is implemente d with each high side power mosfet. since this current is a small fraction of the output current there is very little additional power dissipation. this current is compared with an internal reference current i ref . when the output current reaches the detection threshold i sover , the ocd comparator signals a fault condition. when a fault condition is detected, an internal open-drain mosfet with a pull- down capability of 4 ma connecte d to the ocd pin is turned on. figure 10 shows the ocd operation. this signal can be used to regulate the output current simply by con necting the ocd pin to the en pin and adding an external r-c, as shown in figure 9 . the off-time before recovering normal operation can be eas ily programmed by means of the accurate thresholds of the logic inputs. i ref and, therefore, the output cu rrent detection threshold, are selectable by the r cl value, following equation 1 and equation 2 : equation 1 i sover = 5.6 a 30% at -25 c < t j < 125 c if r cl = 0 ? (progcl connected to gnd) equation 2 i sover = 10% at -25 c < t j < 125 c if 5 k ? < r cl < 40 k ? figure 11 shows the output current protection threshold versus r cl value in the range 5 k ? to 40 k ? . table 6. truth table inputs outputs en in1 in2 out1 out2 l x (1) 1. x = do not care. x (1) high z (2) 2. high z = high impedance output. high z (2) h l l gnd gnd h h l v s gnd h l h gnd v s h h h v s v s 22100 r cl ----------------
circuit description l6206q 12/27 docid022028 rev 3 the disable time (t disable ), before recovering normal operation, can be easily programmed by means of the accurate thresholds of th e logic inputs. it is affected either by c en or r en values and its magnitude is reported in figure 12 . the delay time (t delay ), before turning off the bridge when an overcurrent has been detected, depends only on the c en value. its magnitude is reported in figure 13 . c en is also used for providing immunity to pi n en against fast transient noises. therefore the value of c en should be chosen as big as possible according to the maximum tolerable delay time and the r en value should be chosen according to the desired disable time. the resistor r en should be chosen in the range from 2.2 k ? to 180 k ? . recommended values for r en and c en are respectively 100 k ? and 5.6 nf which allow a 200 s disable time to be obtained. figure 9. overcurrent protection simplified schematic $0y 29(57(03(5$785( , 5() , $ , $ q , $ q 32:(56(16( fhoo 32:(56(16( fhoo 32:(5'026 qfhoov 32:(5'026 qfhoov +,*+6,'('026v2) 7+(%5,'*($ 287 $ 287 $ 96 $ , $ , $ , $ q 2&' &203$5$725 72*$7( /2*,& ,17(51$/ 23(1'5$,1 5 '621 7<3 & (1 5 (1 (1 $ 9 ?&ru/2*,&
docid022028 rev 3 13/27 l6206q circuit description 27 figure 10. overcurrent protection waveforms figure 11. output current protection threshold versus r cl value am02564v1 i sover i out v th(on) v th(off) v en(low) v dd t ocd(on) t d(on)en t en(fall) t en(rise) t disable t delay t ocd(off) t d(off)en v en bridge on off ocd on off am02565v1 5k 10k 15k 20k 25k 30k 35k 40k 0 0.5 1 1.5 2 2.5 3 3.5 5 r cl [ ] 4 4.5 i sover [a]
circuit description l6206q 14/27 docid022028 rev 3 figure 12. t disable versus c en and r en (v dd = 5 v) figure 13. t delay versus c en (v dd = 5 v) 4.4 thermal protection in addition to overcurrent detection, the l6 206q device integrates a thermal protection for preventing device destruction in the case of junction overtemperature. it works by sensing the die temperature by means of a sensitive element integrated in the die. the device switches off when the junction temperature reaches 165 c (typ. value) with 15 c hysteresis (typ. value). & (1 >q )@ w ',6$%/( >?v@ 5 (1 5 (1 5 (1 5 (1 &>q w ',6$%/( >?v@ 5 (1 5 (1 5 (1 5 (1 $0 & (1 >q)@ w '(/$< > $0
docid022028 rev 3 15/27 l6206q application information 27 5 application information a typical application using the l6206q device is shown in figure 14 . typical component values for the application are shown in table 7 . a high quality ceramic capacitor in the range of 100 to 200 nf should be placed between the power pins (vs a and vs b ) and ground near the l6206q to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. the capacitors connected from the en a /ocd a and en b /ocd b nodes to ground set the shutdown time for bridge a and bridge b respectively when an overcurrent is detected (see section 4.3: non-dissipative overcurrent detection and protection ). the two current sources (sense a and sense b ) should be connected to power ground with a trace length as short as possible in the layout. to increase noise immunity, unused logic pins are best connected to 5 v (high logic level) or gnd (low logic level) (see table 3. ). it is recommended to keep power ground and signal ground separated on the pcb. table 7. component values for typical application component value c 1 100 ? f c 2 100 nf c boot 220 nf c p 10 nf c ena 5.6 nf c enb 5.6 nf c ref 68 nf d 1 1n4148 d 2 1n4148 r cla 5 k ? r clb 5 k ? r ena 100 k ? r enb 100 k ? r p 100 ?
application information l6206q 16/27 docid022028 rev 3 figure 14. typical application note: to reduce the ic thermal resistance, and th erefore improve the dissipation path, the nc pins can be connected to gnd. 287 $ /2$' $ /2$' % 95() $ 95() % 287 $ *1' 5& $ 287 % 287 % 96 $ 32:(5 *5281' 6,*1$/ *5281' 9 6 9 '& 96 % 9&3 9%227 & 3 & %227 5 3 ' ' & & 6(16( $ 5 6(16($ ,1 $ ,1 $ ,1 $ ,1 $ (1 $ (1 % & (1% 5 (1% 5 (1$ (1 $ (1 % 9 5()$ 9 9 5()% 9 ,1 % ,1 % ,1 % ,1 % 6(16( % 5 6(16(% & $ 5 $ & 5()$ & 5()% & (1$ 5& % & % 5 % $0y
docid022028 rev 3 17/27 l6206q paralleled operation 27 6 paralleled operation the outputs of the l620 6q device can be paralleled to incr ease the output current capability or reduce the power dissipation in the device at a given current level. it must be noted, however, that the internal wire bond connection s from the die to the power or sense pins of the package must carry cu rrent in both of the associated half bridges. when the two halves of one full bridge (for example out1 a and out2 a ) are connected in parallel, the peak current rating is not increased as the total current must still flow through one bond wire on the power supply or sense pin. in addition, the overcurrent detection senses the sum of the current in the upper devices of each bridge (a or b) so connecting the two halves of one bridge in parallel does not increase the overcurrent detection threshold. for most applications the recommended configurat ion is half bridge 1 of bridge a paralleled with the half bridge 1 of bridge b, and the same for the half bridges 2, as shown in figure 15 . the current in the two devices connected in parallel share well as the r ds(on) of the devices on the same die is well matched. when connected in this configuration the overcurrent detection circuit, which senses the current in each bridge (a and b), senses the current in the upper devices connected in parallel independently and the sense circuit with the lowest threshold trips first. with the enable pins con nected in parallel, the first detection of an overcurrent in either upper dmos device turns off both bridges. assuming that the two dmos devices share the current equally, the re sulting overcurrent detection threshold is twice the minimum threshold set by the resistors r cla or r clb in figure 15 . it is recommended to use r cla = r clb . in this configuration the resulting br idge has the following characteristics. ? equivalent device: full bridge ? r ds(on) 0.15 ? typ. value at t j = 25 c ? 5 a max. rms load current ? 11.2 a max. ocd threshold
paralleled operation l6206q 18/27 docid022028 rev 3 figure 15. parallel connection for higher current to operate the device in parallel and maintain a lower overcurrent threshold, half bridge 1 and the half bridge 2 of bridge a can be connected in parallel and the same is done for bridge b, as shown in figure 16 . in this configuration, the peak current for each half bridge is still limited by the bond wires for the supply and sens e pins so the dissip ation in the device is reduced, but the peak current rating is not increased. when connected in this configuration the over current detection circuit, senses the sum of the current in upper devices connected in pa rallel. with the enable pins connected in parallel, an overcurrent turns off both bridges. since the circuit senses the total current in the upper devices, the ov ercurrent threshold is equal to the threshold set by the resistor r cla or r clb in figure 16 . r cla sets the threshold when outputs out1a and out2a are high and resistor r clb sets the threshold when outputs out1 b and out2 b are high. it is recommended to use r cla = r clb . in this configuration, th e resulting bridge has the following characteristics. ? equivalent device: full bridge ? r ds(on) 0.15 ? typ. value at t j = 25 c ? 2.5 a max. rms load current ? 5.6 a max. ocd threshold $0y & 3 & %22 7 5 3 ' ' & 287 $ /2$' 2&' $ 2&' % 287 $ *1' 352*&/ $ 287 % 287 % 96 $ 32:(5 *5281' 6,*1$/ *5281' 9 6 9 '& 96 % 9&3 9%22 7 & 6(16( $ ,1 ,1 $ ,1 % (1 $ (1 % 5 (1 (1 ,1 % ,1 $ ,1 6(16( % 5 &/$ & (1 352*&/ % 5 &/%
docid022028 rev 3 19/27 l6206q paralleled operation 27 figure 16. parallel connection wi th lower overcurrent threshold it is also possible to parallel the four half bridges to obtain a simple half bridge as shown in figure 17 . in this configuration the overcurrent threshold is equal to twice the minimum threshold set by the resistors r cla or r clb in figure 17 . it is recommended to use r cla = r clb . the resulting half bridge has the following characteristics. ? equivalent device: half bridge ? r ds(on) 0.075 ? typ. value at t j = 25 c ? 5 a max. rms load current ? 11.2 a max. ocd threshold $0y & 3 & %227 5 3 ' ' & 287 $ /2$' 2&' $ 2&' % 287 $ *1' 352*&/ $ 287 % 287 % 96 $ 32:(5 *5281' 6,*1$/ *5281' 9 6 9 '& 96 % 9&3 9%227 & 6(16( $ ,1 $ ,1 $ ,1 $ (1 $ (1 % & (1 5 (1 (1 ,1 % ,1 % ,1 % 6(16( % 5 &/$ 352*&/ % 5 &/%
paralleled operation l6206q 20/27 docid022028 rev 3 figure 17. paralleling the four half bridges $0y & 3 & %227 5 3 ' ' & 287 $ /2$' 2&' $ 2&' % 287 $ *1' 352*&/ $ 287 % 287 % 96 $ 32:(5 *5281' 6,*1$/ *5281' 9 6 9 '& 96 % 9&3 9%227 & 6(16( $ ,1 ,1 $ ,1 $ (1 $ (1 % & (1 5 (1 (1 ,1 % ,1 % 6(16( % 5 &/$ 352*&/ % 5 &/%
docid022028 rev 3 21/27 l6206q output current capability and ic power dissipation 27 7 output current capability and ic power dissipation figure 18 and figure 19 show the approximate relation between the output current and the ic power dissipation using pwm current contro l driving two loads, for two different driving types: ? one full bridge on at a time ( figure 18 ) in which only one load at a time is energized. ? two full bridges on at the same time ( figure 19 ) in which two loads at the same time are energized. for a given output current and driving type the power dissipated by the ic can be easily evaluated, in order to establish which package should be used and how large the onboard copper dissipating area must be in order to guarantee a safe operating junction temperature (125 c maximum). figure 18. ic power dissipation vs. output current with one full bridge on at a time figure 19. ic power dissipation vs. output curren t with two full bridges on at the same time $0y 1r3:0 i 6: n+]vorzghfd\ 7hvwfrqglwlrqv vxsso\yrowdjh 9 , $ , % , 287 , 287 3 ' >:@ , 287 >$@ 21()8//%5,'*(21 $7 $7,0( $0y 1r3:0 i 6: n+]vorzghfd\ 7hvw frqglwlrqv vxsso\yrowdjh 9 , $ , % , 287 , 287 3 ' >: @ , 287 >$ @ 7:2)8//%5,'*(621 $7 7+(6$0(7,0(
thermal management l6206q 22/27 docid022028 rev 3 8 thermal management in most applications the power di ssipation in the ic is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. therefore, it must be taken into account very carefully. beside s the available space on the pcb, the right package should be chosen considering the powe r dissipation. heat sinking can be achieved using copper on the pcb with proper area and thickness. table 8. thermal data symbol parameter package typ. unit r thja thermal resistance junction-ambient vfqfpn48 (1) 1. vfqfpn48 mounted on eval6208q rev. 1.1 board (see eval6208q databrief): four-layer fr4 pcb with a dissipating copper surface of about 45 cm 2 on each layer and 25 via holes below the ic. 17 c/w
docid022028 rev 3 23/27 l6206q electrical characteristics curves 27 9 electrical characteristics curves figure 20. typical quiescent current vs. supply voltage figure 21. typical high-side r ds(on) vs. supply voltage figure 22. normalized ty pical quiescent current vs. switching frequency figure 23. normalized r ds(on) vs. junction temperature (typical value) figure 24. typical low-side r ds(on) vs. supply voltage figure 25. typical drain-source diode forward on characteristic ,t>p$@ 9 6 >9@ i vz n+] 7 m ?& 7 m ?& 7 m ?& $0y $0y 5 '621 > @ 9 6 >9@ 7 m ?& $0y ,t,tdwn+] i 6: >n+]@ $0y 5 '621 5 '621 dw?& 7m>?&@ $0y 5 '621 > @ 9 6 >9@ 7 m ?& $0y 6' >$@ 9 6' >p9@ 7 m ?&
package information l6206q 24/27 docid022028 rev 3 10 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com . ecopack is an st trademark. figure 26. vfqfpn48 (7 x 7 x 1.0 mm) package outline
docid022028 rev 3 25/27 l6206q package information 27 table 9. vfqfpn48 (7 x 7 x 1.0 mm) package mechanical data symbol dimensions (mm) min. typ. max. a 0.80 0.90 1.00 a1 0.02 0.05 a2 0.65 1.00 a3 0.25 b 0.18 0.23 0.30 d 6.85 7.00 7.15 d2 4.95 5.10 5.25 e 6.85 7.00 7.15 e2 4.95 5.10 5.25 e 0.45 0.50 0.55 l 0.30 0.40 0.50 ddd 0.08
order codes l6206q 26/27 docid022028 rev 3 11 order codes 12 revision history table 10. ordering information order codes package packaging l6206q vfqfpn48 7 x 7 x 1.0 mm tray L6206QTR tape and reel table 11. document revision history date revision changes 15-nov-2011 1 first release 10-jun-2013 2 unified package name to ?vfqfpn48? in the whole document. corrected headings in table 1 and table 2 (replaced ?parameter? by ?test condition?). updated table 4 (added subscripts to ?i f ? and ?r opdr ?). added titles to equation 1 and equation 2 and cross-references in section 4.3: non-dissipative overcurrent detection and protection . corrected unit in ta ble 7 (row c 1 ). updated figure 13 (added subscripts to ?t delay ? and ?c en ?). added table 8: thermal data in section 8: thermal management . updated section 10: packa ge information (modified titles, reversed order of figure 26 and table 9 ). minor corrections throughout document. 01-aug-2013 3 updated figure 1 on page 1 . corrected note 1. below table 8 on page 22 .
docid022028 rev 3 27/27 l6206q 27 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not authorized for use in weapons. nor are st products designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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